The invention lies in the semiconductor technology field. More specifically, the invention relates to a configuration and a method for storing the test results of a semiconductor chip having a memory device, whereby the test results are obtained by a BIST circuit.
Integrated circuits and especially memory devices which are implemented in a semiconductor chip are conventionally tested with the aid of a BIST circuit (BIST=Built-In-Self-Test) with regard to their functionality. The results obtained in the course of such investigations with the aid of the BIST circuit contained in the semiconductor chip are stored in an additional SRAM (static RAM) on the semiconductor chip. In other words, another SRAM has additionally been provided heretofore on the semiconductor chip in order to store the test results obtained by the BIST circuit, for example before the results are read out prior to the conclusion of a testing sequence.
The additional SRAM requires space on the semiconductor chip which cannot then be utilized for other purposes. External storage of the test results is also not very helpful since this is associated with additional outlay stemming simply from the fact that external SRAMs have to have contact made with them and be connected separately.
It is accordingly an object of the invention to provide a configuration and a method for storing the test results obtained by a BIST circuit, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows the test results to be stored without an additional area requirement or external storage devices.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor configuration, comprising a semiconductor chip having a memory device with sense amplifiers, a BIST circuit for testing the semiconductor chip connected to the memory device, whereby test results of the semiconductor chip obtained by the BIST circuit are stored in the sense amplifiers of the memory device.
In accordance with an added feature of the invention, the BIST circuit processes test programs and test programs for the BIST circuit are stored in the sense amplifiers.
With the above and other objects in view there is also provided, in accordance with the invention, a method of storing test results of a semiconductor chip having a memory device with sense amplifiers, the method which comprises testing the semiconductor chip with a BIST circuit to obtain test results, and storing the test results obtained with the BIST circuit in the sense amplifiers of the memory device.
In other words, the objects are satisfied by storing the test results in the sense amplifiers of the memory device itself. The test programs for the BIST circuit can also be stored in these sense amplifiers.
The present invention thus uses the sense amplifiersxe2x80x94which are present in any casexe2x80x94of a memory device realized in a semiconductor chip for storing the test results and/or the test programs of BIST circuits.
The invention takes a completely different path from the prior art: instead of an SRAM which can be realized in the semiconductor chip itself or else externally, the sense amplifiers of the memory device realized in the semiconductor chip are used to store the test results of the BIST circuit. A not inconsiderable saving in terms of area can thus be obtained: this is because no additional SRAMs are required for storing the test results of the BIST circuit. Rather, the test results are stored in the sense amplifiers already present, with the result that a memory device configuration that is neutral in respect of area is thus possible. Specifically, no additional outlay at all is required in order to be able to store these measurement results.
In accordance with a concomitant feature of the invention, there is claimed the use of the sense amplifiers of a memory device realized in a semiconductor chip for storing the test results and/or the test programs of a BIST circuit.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration and method for storing the test results obtained by a BIST circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.